Intel at IDF Details Power-Saving, Performance Changes in Skylake CPUs

Posted by at 9:50 am on August 19, 2015

Intel has revealed more details about the capabilities of its upcoming Skylake processor line, though stopped short of giving specific information for processors it will be releasing in the future. Explained to developers and hardware vendors at the Intel Developer Forum, Skylake will feature not only performance and power management improvements, but also bring in extra features, such as enabling a notebook to be woken by a verbal command.
Skylake will offer more frequency adjustments to various parts of the processor, reports Ars Technica, with Intel’s Speed Shift Technology taking it to the extreme. Current power management is split between both the processor and the operating system, with the latter selecting from a range of frequencies offered by the processor depending on the current workload and other factors. Under Skylake, the operating system can force lower frequencies to save battery life, but the processor has greater control in selecting the frequency, making it more responsive to workload changes.

Another power-saving function added in Skylake is duty cycling, which allows the processor to reduce down to the most efficient frequency then cycle between it and a suspended state. This theoretically saves more power than the current system, which suffers from leakage when the processor reaches its lower frequency settings. A new dedicated video codec hardware will also be introduced in the Skylake GPU, letting it use less power when processing H.265/HEVC content.

Intel has yet to advise how much in the way of power savings consumers can expect from the Skylake chip, but earlier leaks suggest notebooks using the processor could enjoy up to 30 percent more battery life than current-generation processors.

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In terms of performance, Skylake benefits from improvements on the eDRAM cache that Intel has been including in some Broadwell processors. Previously, core pairs had 1.5MB of level 3 cache, with the eDRAM used as a 128MB level 4 cache. Under Skylake, the level 3 cache is now 2MB per core pair, and the eDRAM-based level 4 cache has been replaced by a “memory slide cache” connected between the integrated memory controller and the system agent, allowing it to cache any data that is required.

Depending on the processor, Skylake chips will be able to fetch and dispatch up to six instructions at the same time, while also increasing its out-of-order buffer from 192 in Haswell to 224 instructions. Prefetching has been optimized so that it is performed less frequently if it isn’t beneficial to the processor. Some instructions have also been upgraded, with AES acceleration triggering a 33 percent improvement in encryption performance in CBC mode, or 17 percent in GCM.

An on-stage demonstration during the IDF keynote showed off one of the functions Skylake’s onboard low-power digital signal processor is able to accomplish. Gizmodo reports a computer running Windows 10 with the processor was woken from hibernation via the command “Cortana, wake up.” It was not advised whether any special audio hardware was required for it to work, but it is likely the same technology could be used for similar purposes in other operating systems and with other software.

So far, Intel has avoided mentioning what Skylake processors it will be releasing and when, aside from two enthusiast-level processors earlier this month.

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